Synthesis of Asynchronous Systems from Data Flow Specifications

This report presents a method for automatic synthesis of asynchronous digital systems from high-level data ow speciications. We present an extended data ow model that accurately reeects the behavior of the asynchronous components so that the data ow spec-iication can be directly mapped into a hardware realization. In addition, we develop a timing model for the basic asynchronous building blocks and show how to derive the timing parameters of a composed system. This timing model can also be used at the data ow level, allowing designers to explore various design alternatives. We then describe a number of applications of the data ow speciication for high-level synthesis such as schemes for resource sharing, local transformations for data ow description optimization, and allocation and sequencing of operations for given resources. Finally, we present two examples, a 16-bit multiplier and a 16-point FIR digital lter, where the number of modules have been altered at the data ow level using this synthesis method. The eeectiveness of the data ow speciication and performance analysis has been demonstrated from the areas and the back-annotated simulation of actual layouts generated using an industrial standard cell library and commercial CAD tools.